How much of the implementation used in actual silicon overlap with their open source cores isn't clear. I was able to figure out where some non-standard CSR bits are located [3].
Personal, I wouldn't recommend buying them, especially not because they are open source. While source code has been published, the source code looks partially generated and at least for a software dev like me, very hard to read.
I would recommend waiting for the RuyiBook [4], which will contain the second generation of the OpenXiangShan core [5], which is developed fully in the open on GitHub. From the information available, it seems likely that it will become available this year and that it would then be the highest performing RISC-V processor generally available. See my old comment for benchmarks I ran in the RTL simulation: https://news.ycombinator.com/item?id=41331786#41331968 The only unfortunate thing it that it will likely lack support for the vector extension.
I hope they follow my suggestion of shipping the processor source code with the default Linux install.
[1] https://github.com/T-head-Semi/openc910
[2] https://github.com/XUANTIE-RV/openc906
[3] https://github.com/camel-cdr/rvv-d1?tab=readme-ov-file#enabl...
[5] https://github.com/OpenXiangShan/XiangShan
See also, slides on the XiangShanV2 microarchitecture: https://raw.githubusercontent.com/OpenXiangShan/XiangShan-do...