Changing the Behavior of a Commercial CPU

I have thought of a idea about that, where the microcode memory has ROM and RAM, and uses a long VLIW transport-triggered (although the address bus and data bus are also registers) self-modifying microcode with Muxcomp and each instruction also is a jump. There is no cache, but you can store stuff in the microcode RAM for temporary use, and there is also no out of order execution or all of that other stuff either. I don't know if there is any such thing, although apparently VAX does at least a few of these things (but not all of them).